The effects of the thickness of the sandwiched layer and of the annealing time on induced nanostructures during solid state dewetting of a metal-semiconductor-substrate triple layer structure

Abstract

A structure made of a very thin Pd metal layer at the surface, followed by a SiC layer of varied thickness were deposited onto a c-Si substrate by e-beam evaporation at room temperature. Solid state dewetting of the top metal layer is achieved at near eutectic temperature of Pd/Si phase at 800 °C and we study its effect on the sandwiched SiC semiconductor layer of varied thicknesses. Scanning electron microscopy (SEM) images showed that the dewetting process accelerates with decreasing the SiC film thickness, whereas the nucleation and shape patterning were found to be less sensitive to the time of anneal in the studied time domain between 30 min – 3 hours. Focused ion beam scanning electron microscopy (FIB-SEM) and Transmission electron microscopy (TEM) analysis revealed the thermally initiated surface dewetting of the Pd metal at the SiC interface as well as an apparent diffusion into this intercalated layer. Large dewetted Pd nanostructures protruding into the c-Si substrate suggest a dewetting effect of the underlying SiC layer from the substrate surface. Rutherford Backscattering Spectrometry (RBS) analysis revealed the diffusion of silicon from the SiC sandwiched layer into the Pd layer during annealing which resulted in the formation of Pd2Si phase, this was also confirmed by X-ray Diffraction (XRD). While the absence of the 800 cm−1 absorption mode in the Fourier transform infrared (FTIR) spectrum of the as-deposited SiC layer suggests a disordered microstructure, a narrow absorption peak that appeared at 796 cm−1 in the annealed samples confirmed the crystallization of the network in SiC bonds.