The effects of annealing encapsulant and ambient on the barrier height of WNx/GaAs contact and self-aligned gate field effect transistor fabrication

Abstract

It was found that the barrier height of thermally stable WNx /GaAs Schottky contacts can be enhanced by a high-temperature annealing technique. In this study, the WNx /GaAs contact was annealed under different conditions including (i) furnace annealing under SiO2 encapsulant with N2 and arsine ambient, (ii) furnace annealing under arsine-overpressure capless annealing, and (iii) rapid thermal annealing (RTA) under SiO2 encapsulant and argon ambient. The temperature range for furnace annealing was 700–850 °C and for RTA, 700–950 °C. RBS analysis of all samples revealed no detectable interdiffusion at the WNx /GaAs interface up to an annealing temperature of 850 °C for furnace annealing and 950 °C for RTA. The Schottky barrier height increased from 0.59 eV, as deposited, to the commonly reported value of 0.72 to 0.74 eV, at the optimum temperatures for all the annealing conditions mentioned, with one exception. Barrier heights as high as 0.8 eV were obtained using furnace annealing under SiO2 encapsulant and arsine ambient. This corresponds to an enhancement up to 80 meV and is significant for improving the noise margin of GaAs integrated circuits, which is typically 200–300 mV. However, such annealing conditions also caused leakage current localized at the perimeter of the WNx /GaAs contact. Such a leakage current can be removed by slight mesa etching of the GaAs at the edges. WNx SAGFET structures were fabricated using both capless furnace annealing in an arsine ambient and RTA in an argon ambient. It was found that capless furnace annealing resulted in significantly better immunity to short-channel effects than that of RTA. Transconductance as high as 300 mS/mm was obtained with a gate length of 0.5 μm.