The effect of underfill on thermal stresses on logic ASIC and its electrical performance

Abstract

Flip chip technology is widely used today to support the demand for high interconnect density of modern microelectronic circuits. Conventionally, solder bumps have provided the electrical and mechanical connection between the chip and the substrate. The solder bumps are prone to fatigue and failure especially in large chips and/or mobile devices. Conventional underfilling process which consists of flowing an epoxy under the chip and curing it after the flip chip connections are made mechanically supports the assembly, significantly reducing the shear stresses on the bumps and minimizing the chip warpage due to thermal stresses. However, underfill also has side effects. The flow of underfill depends on a lot of parameters usually can be incomplete or containing a lot of voids, inconsistent underfill results in unpredictable overall durability or manufacturing survivability. Furthermore, underfilling introduces certain components of stress, this form of stress can have adverse effect on the electrical performance of the die if it occurs close to stress sensitive parts. In this study, the effect of underfilling and its quality on the clock frequency shift of a DSP (Digital Signal Processor) chip used by Starkey Hearing Technologies is investigated. Clock frequency measurements after a solder reflow process has been compared for different underfill materials, and underfill quality. Finite element analysis was implemented to assess the stress transferred to the clock circuit on the die and examine how existence of underfill, bump height, location of bumps, and underfill voids affect the stress. The following results have been concluded based on the work presented in this paper:The conventional underfilling process for dies with very small standoff heights can be very in consistent, strongly depending on the gap uniformity, flex traces, cleanliness of the package after solder reflow, etc. large percentage of delamination and voids can occur. The voids and delamination can cause solder extrusion as well as inconsistent stress distribution on the die.Although underfilling causes large normal stresses on the die, it reduces the effective stress on the die which can translate to less warpage and the problems associated with it.The height of the bumps does not strongly affect the amount of stress build up on the die if it does not compromise a uniform underfill.Relocation of the bumps away from the clock circuit significantly reduces the stress on the clock, and it has been shown to minimize the clock shift in practice. A minimum amount of distance between the clock circuit and solder bumps should be considered when DSP layout are designed.If the clock circuit surface is not in contact with the underfill, normal stresses will not be transferred to the clock circuit minimizing the clock frequency shift. The best approach to implement this method is wafer-level underfill technique. The underfill will be applied at the wafer fab and precision lasers can cut the underfill laminate at desired locations. This process can guarantee support for the die by a uniform underfill, while stress sensitive parts will be protected against unwanted thermal stresses.