The Effect of Spacer Thicknesses on Si-Based Resonant Interband Tunneling Diode Performance and Their Application to Low-Power Tunneling Diode SRAM Circuits

Abstract

Si-based resonant interband tunneling diodes (RITD) with spacer thicknesses varying from 1 to 16 nm were grown and fabricated. The effect of spacer thickness on the peak-to-valley current ratio (PVCR), peak current density Jp, and voltage swing was studied. By increasing the tunneling spacer thickness up to 16 nm, RITDs with a J p of as low as 20 mA/cm2 with an associated PVCR of 1.6 were obtained, which are suitable for low-power tunnel diode SRAM applications. With the previously reported highest RITD Jp of 218 kA/cm2, a Jp spanning nearly seven orders of magnitude can be obtained by engineering the tunneling spacer thickness and doping densities, thus demonstrating tremendous flexibility to optimize Jp for different circuit applications (logic, memory, and mixed-signal). Using a low-current-density RITD developed in this paper, a bread-boarded one-transistor tunneling-based SRAM (TSRAM) memory cell with low standby power consumption was demonstrated. This is the first report of a Si-based TSRAM memory circuit using Si-based RITDs. The result demonstrates the potential of Si-based tunnel diodes for low-power memory applications