Abstract
Metal-insulator-semiconductor field-effect transistors (MISFETs) with high-k HfN <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> multilayer gate dielectrics fabricated with Si surface flattening process were investigated. The Si surface flattening process was carried out by Ar/1.0%H <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> annealing for 30 min. A higher I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> on</sub> / I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> off</sub> current ratio was obtained by increasing the number of HfN <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> gate dielectric layers while its characteristics such as drain current, saturation mobility and subthreshold swing (SS) are not markedly degraded. This is attributed to the thicker gate dielectrics. Furthermore, it is found that these characteristics are found to be effectively improved by Si surface flattening process.
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