The Effect of Shared L2 Cache on Determinism in Airborne Embedded System

Abstract

Multicore processors have absolutely advantages over single-core processor in following aspects: performance, power, volume and weight. These advantages lead the application of multicore processors in airborne embedded system to be inevitable. But the multicore is not everything, there exist a lot of hardware interferences. Among them the shared L2 cache has been identified as one of the major sources of contention between threads. To eliminate the interferences caused by L2 cache, we assign the shared cache to each core. But this will make the shared cache inefficient. In this paper, we analyze the effect of L2 cache on determinism in airborne embedded system and propose a cache partitioning algorithms which will eliminate the interferences and also make the L2 cache more efficient.