The effect of inserted SiO2 thickness on memory characteristics for nonvolatile memory with stacked trapping layer

Abstract

Memory capacitors with stacked Zr0.5Si0.5O2/SiO2/Zr0.5Si0.5O2/SiO2/Zr0.5Si0.5O2 trapping layers are fabricated, and the effect of inserted SiO2 thickness on memory characteristics is investigated. It is observed that the electric field across the tunneling layer, electrostatic repulsive forces between adjacent interfaces, electron tunneling thickness, occupied probability of traps and temperature jointly contribute to the memory characteristics, and the optimal thickness should be in the range of 1.3–1.7 nm, taking into consideration the trade-off between memory window, program/erase speed and data retention characteristics. In the aspect of selecting inserted layer thickness, the result provides useful references for future charge trapping memory applications.