The effect of high-k gate dielectrics on device and circuit performances of a junctionless transistor

Abstract

The impacts of high-k gate dielectric permittivity on the device and circuit performances of a double-gate junctionless transistor (DGJLT) are studied with the help of extensive device simulations. The results are compared with a conventional inversion mode double-gate metal oxide semiconductor field effect transistor (DG MOSFET) of same dimension. Drain induced barrier lowering, intrinsic gain $$(G_{m}R_{O})$$(GmRO), and unity gain cut-off frequency $$(f_{T})$$(fT) are degraded with an increase in gate dielectric permittivity $$(k)$$(k). The transconductance $$(G_{m})$$(Gm) and gate capacitance $$(C_{GG})$$(CGG) are slightly affected with increase in $$k$$k. The gain of CMOS single stage amplifier and delay of inverter are found to be decreasing and increasing, respectively, with increase in $$k$$k. In order to mitigate these short channel effects due to the high-k gate dielectrics, a hetero-gate-dielectric structure with symmetric double-gate junctionless transistor (HG-DGJLT) is studied. HG-DGJLT offers superior $$G_{m}, \, C_{GG}$$Gm,CGG and $$f_{T}$$fT compared to $$\hbox {SiO}_{2}$$SiO2-only and $$\hbox {HfO}_{2}$$HfO2-only DGJLT. However, intrinsic gain of HG-DGJLT is inferior to $$\hbox {SiO}_{2}$$SiO2-only and $$\hbox {HfO}_{2}$$HfO2-only DGJLT.