The effect of gate dielectric deposition at different vacuum conditions on the field-effect mobility of pentacene based organic field effect transistors

Abstract

Pentacene based organic field effect transistors with polyvinyl phenol gate dielectric are fabricated by controlling the dielectric surface energy and grain size of the first monolayer of pentacene. In this work, we introduce a novel approach to tune the surface energy of the polymer dielectric. This is performed by baking the polymer dielectric, polyvinyl phenol, at different vacuum conditions at 160°C before the deposition of pentacene layer. After the deposition of pentacene, these devices exhibit dramatic improvement of carrier mobility and an extraordinary change in electrical characteristics. This includes an enhancement of carrier mobility as high as 400% increase from 0.53cm2/Vs for low vacuum (high surface energy of the gate dielectric) to 2.02cm2/Vs for high vacuum (low surface energy of the gate dielectric) baking of polyvinyl dielectric thin film. It has been observed from the atomic force microscopy that the carrier mobility has a one to one correspondence with the grain size of the first monolayer. That is the carrier mobility increases with the increase in grain size. This fact is further interpreted in terms of the trap limited transport model proposed by Horowitz et.al.