The Effect of Dual Dummy Gate in the Drift Region on the on-State Performance of SOI-LDMOS Transistor for Power Amplifier Application

Abstract

The present work proposes a novel dual dummy gate Silicon-on-Insulator Laterally Double Diffused Metal-Oxide-Semiconductor (SOI-LDMOS) transistor. TCAD simulation shows considerable promise to enhance the dc, analog/RF, and switching performance than the single dummy gate and conventional SOI-LDMOS transistor. A strong accumulation region (SAR) forms under the optimum biased dummy gates (at the semiconductor surface in the drift region) that assist in increasing the On-current and, thereby, reducing the On-Resistance. The proposed device exhibits ~93.5% improvement in On-current (ION), ~144% increase in transconductance (gm), ~29% reduction in specific On-resistance (RON,sp), ~360% improvement of intrinsic gain compared to the conventional SOI-LDMOS transistor. The dummy gates, which are in short with the source contact at zero potential, act as a field plate, and minimize the gate to drain capacitance due to the shielding effect. Improvement in the cut-off frequency (fT) and the maximum frequency (fMAX) is reported. The proposed device also offers a decrease of the gate to drain charge (QGD) leading to reduction in Figure of Merit RON,sp × QGD by ~31%. The increase of maximum power per unit area by ~52% is reported for power amplifier applications. It is shown that improving the On-State performance by tuning the dummy gate bias gives a simple, new, and cost-effective technology solution for power electronics applications.