Abstract

The four step technology of precise anisotropic plasma etching of Silicon under e-beam lithography and then isotropic wet etch removal of defected surface layer of Silicon oxidized by RTP was developed in order to fabricate suspended planar silicon nanowire (Si- NW) arrays. As a result the Silicon nanowires with CD up to 8 nm and size of 150–1000 nm on SOI wafer were made and investigated. The distribution of defects in surface layer caused by ion bombardment during plasma etching was simulated by Monte Carlo model. Electrical conductivity of fabricated Si-NW arrays before and after damaged layer removal was measured by probes with pseudo-FET configuration. It was found that after removal of that layer from surface the conductivity of Si-NW increases by 6 orders of magnitude. This effect solely attributed to dramatic decreasing of carriers scattering on defects on surface damaged layers.

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