The Effect from Finite DC Gain and Gain-Bandwidth of an Op-amp on Pipelined Analog-to-Digital Converter Errors

Abstract

Pipelined ADCs with digital error correction and double-sampling are demand gain error of the stage calculations at given parameters of the op-amp of the stages. In contrast to known approaches to the analysis of the 1.5-bit conversion stage, results within the z-domain with account for both the finite GB and DC gain are discussed. This analysis allows us to more accurately take into account GB and DC gain dependencies versus ADC resolution and sampling rate for both conventional and double-sampling stages of the pipeline.