The Differentiating Correction Circuits in Complementary Buffer Amplifiers

Abstract

_ It is shown that the performance of the ICs of complementary buffer amplifiers (BA) widely used as drivers of cable communication lines in devices of radio engineering and telecommunications is significantly influenced by parasitic capacitances (C p1 , C p2 ) in the emitter circuits of the input voltage followers and reduced to the load capacitance C p1 (C p2 ). This limits the maximum slew rate (SR), which becomes small at the BA low power consumption in the static mode. The authors propose a method for the SR increasing in the micro-power BAs by introducing special differentiating circuits into the BA classical scheme for the transient correction. It is established that the recommended options of differentiating capacitor connections allow the generation of additional recharge currents of parasitic capacitances C p1 (C p2 ), thus improving the SR and reducing the transient time. The results of computer simulation of the BA for BJT of the complementary technological process of JCT “SPE Pulsar” (Moscow), and also on the transistors of the analogue array chip ABMK_1.7, show that the SR of complementary BA increases more than 10 times to 20000 V/°s (at a current of consumption Ip = 500 °A, including when operating in the low temperature range and exposure to radiation.