Abstract
This paper presents a hardware architecture developed for use with real-time Chain Code. This system applies open-chain code and closed-chain code to solve some problems related to noise and an inexact edge image. The design of the proposed method uses the Verilog HDL (Hardware Description Language) for the dedicated hardware architecture on a pipeline architecture. The hardware architecture is implemented using Virtex5 (xc5vlx330) on Xilinx Field Programmable Gate Arrays (FPGA). The results of the analysis show that this implementation can achieve a maximum operating frequency of 74.74 MHz and possesses adequate performance to process a 640x480 (VGA) resolution image.
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