Abstract
Presents two-level pipelined systolic arrays for high throughput IIR filters. By combining the look-ahead schemes and the two-level pipelining technique, the VLSI architectures which support the maximum throughput rate and the strategies which make this rate possible are derived. Extending the results concluded from 1-D IIR filters, the authors also present high throughput rate realizations for 2-D IIR filters. >
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