The design related issue debug by static fault isolation methodology

Abstract

As semiconductor technology keeps developing, failure analysis and device characterizations become more and more challenging. Global fault isolation without detailed circuit information comprises the majority of foundry EFA cases. That's why static fault isolation is majority part of the foundry EFA methodology. Limited pins will be biased with the static condition to access and trigger the defect, finally visualize it. Since the limited access pin and info were provided the static fault isolation has its intrinsic limitation, especially for the functionally failed unit analysis. So the different indirect methodologies were applied in the static analysis. The conventional and straightforward practice is to adjust the different bias condition to access and trigger the detect, trial and error. The other method is trying to select suitable and representative units for analysis. As long as some signal was triggered the subsequent analysis can be proceed on. For the functional fail the situation will be even worse because the failure mode is difficult to verify by the DC bias condition. In this paper a functional fail prototype issue was analyzed. DC bias shows normal for the units which customer's feedback show leakage under the functional testinge After the studying of the customer provided layout and circuit of the suspected block, we repetitively switch on and off of the power we biased on some of the pin. We manage to trigger the leakage mentioned by customer. With this kind of leakage hot spot was successfully observed. Combined with different hot spot of different bias condition and layout/circuit study, the failure mechanism was come out. It is a design related problem which was also accepted by the designer.