The Design of Background Subtraction on Reconfigurable Hardware

Abstract

Moving object detection is a very important research topic for video surveillance. Drawbacks of low computational efficiency and high power consumption are still challenging to current background subtraction methods. This paper proposes a hardware design to accelerate background subtraction. A real-time background subtraction method is designed with function and task partitions to improve throughput, and implemented with Verilog HDL on FPGA. The design parallelizes the computations of background update and subtraction with seven-stage pipeline of three-clock latency. Only two frame buffers have to be used in the design. Simulation results for videos of 640x480 resolution on a low-end FPGA device show 368 fps throughput for only the real-time background subtraction module, and 56 fps for the whole system including off-chip memory access. Real-time efficiency with low power consumption and low resource utilization has been demonstrated.