The design of an area efficient segmented DAC

Abstract

DAC architectures reported in the literature use segmentation schemes involving more thermometer and less binary bits, in order to guarantee a better dynamic and static performance. In this paper, a novel technique is proposed to minimize the glitch in the binary section of a segmented current steering DAC through the custom design of latches. This enables more bits in the binary section of the segmented DAC than what is reported in the literature. Using the proposed technique, a 12 bit 400MSPS current steering DAC with 8 bit binary section and 4 bit thermometer section is designed using AMI 350 nm n-well CMOS process. A 12 bit segmented DAC with 8 MSB thermometer section and 4 binary section is also designed using the conventional approach. The static and dynamic performance of the above two segmented DACs are obtained through ELDO SPICE simulations. From these, it is found that the INL, DNL and SFDR at 1 MHz for the proposed DAC are 0.7 LSB, 0.65 LSB and 79 dB whereas those of the conventional segmented architecture are 0.63 LSB, 0.04 LSB and 87 dB respectively. With only marginal degradation in the static and dynamic performance, the proposed DAC results in lower silicon area and routing complexity. The reduction in the digital decoder area and the no. of latches required for the proposed DAC enables higher update rate for the DAC. The estimated area of the proposed DAC is about 30% times less than that using the conventional segmentation scheme.