The design of a memory controller for DDR SDRAM

Abstract

Memory system performance is an important factor in determining overall system performance. The design of key components of the memory system, such as the memory controller, becomes more important as memory performance becomes a limiting factor in high performance computing. This work focuses on the design of a unit which sends control signals to Double Data Rate Synchronous Dram (DDR SDRAM). The design is based on established concepts such as access reordering. A novel, adaptive page policy based on a machine learning algorithm has been developed in this work and evaluated with traditional page policies. the work illustrates some of the design trade-offs in a memory controller and the performance of the designs when using real application address traces.The results show that access reordering improves the performance of DDR SDRAM compared to in-order scheduling (up to 50% improvement) and that scheduling multiple requests can result in latency hiding. The dynamic page policy approximates the best static page policy in most cases.