The design of a low-complexity systolic architecture for fast bit-parallel exponentiation in a class of GF(2/sup m/)

Abstract

Recently, bit-parallel architecture for hardware implementation in GF(2/sup m/) is of practical concern. We present a new inner product multiplication algorithm that is an alternative develop in a polynomial basis for the field GF(2/sup m/) generated by an irreducible all one polynomial (AOP). The algorithm is more efficient to construct a low-complexity bit-parallel architecture for computing AB multiplication. The complexity of the designed multiplier only requires the latency of m+2 clock delays and the complexity of basic cell comprises one 2-input AND gate, one 2-input XOR gate, and four latches. Meanwhile, the designed multiplication tree, based on the characteristic of a binary tree, uses the ideal AB multiplier to compute exponentiation in GF(2/sup m/). The latency of exponentiation only requires (m+2)[log/sub 2/m]+1 clock cycles. The cyclic time (a clock period) of our presented architectures desires one-gate delay. For the computing exponentiation in GF(2/sup m/), it turns out that our designed exponentiation is more efficient as it leads to simpler architecture and accelerates computation.