The design of a high-performance cache controller: a case study in asynchronous synthesis

Abstract

Because of ever-increasing demands on digital system performance, there is a need for new architectures which fully exploit the capabilities of contemporary VLSI technology. Asynchronous or self-timed systems, in particular, promise a number of advantages over traditional synchronous systems: adaptive operation (based on voltage, temperature, process and data), wider environmental operating range, reduced power consumption, and robust interfaces. This paper integrates two distinct areas in asynchronous system design: the design of controllers and the design of processor architectures. In [27], we presented a new method for the synthesis of locally-clocked asynchronous controllers. In [12], the STRiP architecture was shown to provide an attractive alternative to comparable synchronous and asynchronous implementations. However, to support this asynchronous paradigm, an efficient asynchronous memory subsystem is critical. In this paper, we apply the locally-clocked synthesis method to the design of an asynchronous second-level cache controller. The paper contains the following new contributions: (1) it demonstrates the feasibility of the proposed locally-clocked method for the design of a substantial real-world controller; (2) it demonstrates in particular how such a controller can support the asynchronous external interface of an asynchronous RISC architecture (e.g. STRiP); and (3) it presents a cache controller which is significantly faster than a comparable synchronous design. Cache-access latency using our design is 50% less than using an equivalent synchronous implementation.