The design considerations of stray inductance for power modules with parallel-connected IGBT chips for a digital gate driver control

Abstract

This paper aims to clarify the effect of asymmetric gate inductance Lg and emitter inductance Le inside power modules with two parallel-connected IGBTs on switching characteristics when a three-step digital gate driver is employed. Five types of IGBT modules with different Lg and Le were fabricated to implement double pulse tests by conventional gate driving and digital gate driving with three-step vectors. Under the conventional gate driving, the asymmetric Le introduced an imbalanced current during on-stage, and the asymmetric Lg introduced gate voltage spike Vg_spike and an imbalanced current during the turn-off interval. Large Lg introduced large Vg_spike. From the miller plateau in the turn-off, the current started to concentrate on the IGBT whose Lg is small. In the turn-on interval, the asymmetric Le made current share in two IGBTs become imbalanced, and the occurred large Vg_spike is positively corresponding to the difference of emitter current Ie flowing through two IGBTs. Under digital gate driving, it was found that the tradeoff between switching loss and voltage/current overshoots can be improved. And, the difference of Eoff between two IGBT chips, which results from asymmetric Le mainly, could be decreased more than that in conventional gate driving. In the turn-on interval, the large Vg_spike can be suppressed by a small vector number at the second step, and the difference of turn-on loss Eon could be also decreased. According to the above switching characteristics, the design considerations of power modules with parallel-connected IGBTs were proposed as the digital gate driver is applied.