The design and realization of CAN bit timing logic

Abstract

In the CAN bus, mistakes in bit timing will lead to serious decline in bus performance. How to deal with the bit timing of CAN bus communication decided whether the CAN controller can receive or transmit data correctly. According to bus protocol, bit synchronization will fix bit errors resulting from improper setting in many cases. This paper illustrated the structure of nominal bit time and the principle of bit synchronization, gave an optimized method of nominal bit time of CAN2.0 protocol, that the four non-overlapping segments of traditional nominal bit time is simplified to 3 non-overlapping segments, and on this basis, proposed a design method of bit timing processor of CAN bus based on the synchronized state machine. It also provides programmable time segments to compensate for the propagation delay times and phase shifts, and gave simulation and verification of the design. The results show that the design work which obeys the CAN2.0 protocol, can more easily deal with the CAN bus communication bit timing, realized the control of CAN bus protocol on the bit timing and bit synchronization, and better optimizes the CAN network.