Abstract
This paper direct to security and real-time requirements in high-speed network transmission processing, based on SOPC technology, design a High throughput AES encryption/ decryption processing unit with pipelining. The design goal is to optimize the hardware structure and improve the throughput, S-box design and parallel processing structure. Compared with traditional AES crypto-chip has faster rate with encryption and less consumption of resources advantages. This design adopts VHDL hardware description language, use Quartus II 8.0 for the synthesis and routing, and this processing unit is packaged an independent IP core, attached to the Altera provided the Nios II system, finally download and test validation on the DE2 development platform.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
