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Abstract
DCT is the most popular image and video coding algorithm, and is widely used. Though the design of common one-dimension DCT only consists of many adders, there are a lot of limitations in the speed of processing data and the possession of system resources. This paper introduces a kind of 8 * 8 two-dimensional DCT optimization design, and implements it in FPGA. By adopting pipeline design, multipliers and adders, we reduce the resources’ possession of FPGA and improve the operational speed. At last we use the simulation by Quartus II and the performance analysis to prove the correctness and effectiveness of the design [1].
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