The data acquisition system of the Belle silicon vertex detector (SVD) upgrade

Abstract

We have developed a new data acquisition system (DAQ) utilizing PC farms for the upgraded silicon vertex detector (SVD2) in the Belle experiment at the KEKB factory. The SVD upgrade will increase the number of readout channels by about 50% to 110592. The maximum trigger rate is also expected to rise to 1.0kHz due to the increasing beam intensity from KEKB. To manage the increased dataflow, we have constructed the DAQ system with twelve Linux PCs, each of which is directly connected to three flash AD converter boards through PCI data I/O boards. The advantages of using the PCs include the ease of software maintenance, market availability of hardware when replacements are needed, scalability and much improved processing speed. In order to decrease the data transfer load to the data storage system, we have developed data sparsification algorithms that calculate pedestal and noise, find particle hit channels and thus reduce the data down to 5% of the original volume. We have measured the data processing speed of the system at various read-out channel occupancy levels. The system is able to process data at a 1.3kHz trigger rate with 5% occupancy and will thus be able to handle the anticipated 1.0kHz trigger rate.