Abstract
The CLEO-III Trigger provides a trigger decision every 42 ns, with a latency of approximately 2.5 /spl mu/s. This paper describes the free-running, pipelined trigger decision logic, the throttling mechanism whereby the data acquisition system can modulate the trigger rate to maximize throughput without buffer overrun, and the subsequent signal distribution mechanism for delivering the trigger decision to the front-end electronics. This paper also describes the multilevel simulation methods employed to allow detailed low-level models of trigger components to be co-simulated with more abstract system models, thus allowing full system modeling without incurring prohibitive computational overheads.
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