The challenges of warpage with thin core substrate for 2.5DIC assembly

Abstract

For 2.5D/3D integrated circuit assembly application, thin core package is one of the important indexes. Comparing with traditional substrate, the benefits of thin core substrate are lower z-height, lightweight, low cost and high performance. However, thin core substrate warpage is the most challenge in assembly process steps. In this study, thin core substrate (<600um in thickness) is used for this thinner package. The warpage of chip module and substrate on carrier are studied by using Shadow Moire technique at 240 degree C. Carriers are studied for chip module bonding to improve the bridge issue during reflow process. The yield loss of bump bridge can be improved and less than 5% after optimization which detected by x-ray. Underfill filling and flowing capability is determined by SAT. Two types of heat sink are evaluated to meet the coplanarity value < 12mil. The maximum coplanarity is about 10mil and CPK is larger than 1.67 by using HS-B. In addition to warpage improvement, the reliability performance is also evaluated for package, such as assembly out time zero, precon, TCG, HTST and uHAST.