The calibration of process window model for 55-nm node

Abstract

In previous OPC model calibrations, most of the work was focused on how to calibrate a model for the best process conditions. With process tolerance decreasing in coming lithography generations, it is increasingly important to be able to predict pattern behavior through process window. Due to a low k1 factor that leads to a smaller process window, the use of process window models is required for both optical proximity correction (OPC) and Lithography Rule Check (LRC) applications to insure silicon success. In this paper, we would try to calibrate multiple process window models. The resulting models will be verified and judged using additional measurement data to demonstrate the quality.