THE BEHAVIOR AND TESTING IMPLICATIONS OF CMOS IC LOGIC GATE OPEN CIRCUITS

Abstract

The electrical and test properties of several logic gate open circuit defect structures were measured. Results indicate that tunneling current across fine geometry discontinuities enables low frequency operation of ICs. No significant capacitive coupling was observed for adjacent metal interconnect or for large metal opens on the gate interconnects. These results indicate the need for different methods of open circuit defect detection during test. I. Introduct ion Structured test methods require thorough knowledge of the defects that cause failure. This study presents data on the electrical characteristics of a common CMOS IC defect, an input open circuit to a logic gate. Individual transistor gate terminal opens are not considered. Data show that logic gate input open circuit defects for narrow interconnect discontinuities allow circuit functionality at frequencies from DC into the MHz region. Evidence supports electron tunneling as the basic mechanism for circuit functionality in the presence of this type of defect. This suggests that the open-circuited logic gate defect should be treated as a delay fault in order to guarantee detection. Open circuit defects with wide dimensions exhibited no signal coupling. Data also show the conditions under which quiescent power supply current (IDD,) tests can detect open circuit logic gate inputs. In the late 1980s two groups fabricated circuits or tested existing circuits with specific types of open circuits [l, 21. Others studied transistor-level open circuit phenomena and proposed design changes to reduce the occurrence of opens [3, 41. It was demonstrated that some open circuits are not detected by conventional stuck-at test methodologies.