The Bang Bang PLL as a Clock Source in Serial-De-Serializer (SERDES) Applications

Abstract

Demands for increased wireline data throughput necessitate multi-GHz clock sources of ever-greater fifidelity. At the same time, there has been resolute industry pressure for process geometry size reduction, digital circuit implementation and modularization to fulfill the objectives of development cost reduction, scalability, increased functionality and decreased power dissipation. In aid of these objectives, this work demonstrates a digital bang-bang phase-locked loop that develops the 14-GHz clock for a 56-Gb/s PAM-4 transceiver. This low jitter clock source is realized using an LC-based digitally-controlled oscillator having a frequency tuning range of 14 % and worst case resolution of 2.0 MHz/LSB. The major digital functions of the band-bang phase-locked loop are consolidated in a single, fully-synthesized digital signal processing unit operated at 3.5 GHz or 10x the reference clock frequency. Limit cycles are minimized, without the aid of a multi- bit time-to-digital-converter, through substantial reduction of loop latency using a look-ahead digital loop fifilter. Various design techniques exploiting an advanced 7-nm FinFET technology are discussed including noise reduction, frequency resolution and tank Q-enhancement. Additionally, methods of accurately modelling a digitally-controlled oscillator and linear loop analysis of the bang-bang phase-locked loop are demonstrated. Closed-loop phase noise performance is accurately predicted using an industry-standard digital event-driven simulator with dramatically reduced computation effort compared to analogue or mixed-mode simulations. Here, a method of faithfully calculating various noise profiles for digitally-controlled and reference oscillators is exploited. The measured RMS random jitter of the BBPLL, integrated from 1 kHz to 100 MHz, is 143 fs and shows limit-cycle free operation resulting in minimal spurious tone activity in the frequency spectrum. The BBPLL consumes 40 mW of power, while the DCO consumes 14.8 mW of this total. The RMS jitter demonstrated in this thesis is consistent or better than analogue charge-pump PLLs of comparable frequency and significantly better than the reported BBPLLs at very competitive area and power dissipation.