The Application of Two-dimensional Cellular Automata in Logic BIST

Abstract

With the increase in complexity of VLSI and the test cost of automatic test equipment (ATE), logic built-in self-test (BIST) has been widely applied. In order to reduce the test time of logic BIST, logic BIST with multiple scan chains has been proposed. However, the main shortcoming of logic BIST with multiple scan chains is low fault coverage (FC). A novel two-dimensional cellular automata (2-DCA), which is called two-dimensional restricted vertical neighbor cellular automata (2-DRVNCA), is proposed to resolve this problem. Using this 2-DRVNCA as pseudorandom test pattern generator (PRPG), high FC can be achieved. In the last, this PRPG is applied on some benchmark circuits of ISCAS'89, and average FC (82% ~ 89%) is obtained.