The analog channel for the readout of the outer layers of the SuperB SVT

Abstract

In this work, we present the design and the results of the analog channel of the readout circuit for the outer layers of SuperB Silicon Vertex Tracker (SVT). In these layers, the strip detectors have a very high stray capacitance and high series resistance. Therefore, the noise optimization was the first priority design concern. To fulfill the noise level and efficiency requirements, a compromise on the best peaking time has been investigated. The ASIC is composed by a classical processing scheme, composed by a preamplifier, shaping amplifier and TOT for the digitalization of the signals. The chosen shaping function is the third-order semi-Gaussian function implemented with complex poles. An inverter stage is employed in the analog channel in order to operate with signals delivered from both p and n strips. The circuit foresees the possibility to select the peaking time of the shaper (250, 375, 500 and 750 ns). In this way, the noise performances and the signal occupancy can be optimized according to the real background during the experiment. The first prototype has been fabricated in the 130nm IBM technology which is considered intrinsically radiation hard. The first results of the experimental characterization of a produced prototype are here presented.