Abstract
Modern experiments search for extremely rare processes hidden in much larger background levels. As the experiment`s complexity, the accelerator backgrounds and luminosity increase we need increasingly complex and exclusive event selection. We present the first prototype of a new Processing Unit (PU), the core of the FastTracker processor (FTK). FTK is a real time tracking device for the ATLAS experiment`s trigger upgrade. The computing power of the PU is such that a few hundred of them will be able to reconstruct all the tracks with transverse momentum above 1 GeV/c in ATLAS events up to Phase II instantaneous luminosities (3 × 1034 cm−2 s−1) with an event input rate of 100 kHz and a latency below a hundred microseconds. The PU provides massive computing power to minimize the online execution time of complex tracking algorithms. The time consuming pattern recognition problem, generally referred to as the ``combinatorial challenge'', is solved by the Associative Memory (AM) technology exploiting parallelism to the maximum extent; it compares the event to all pre-calculated ``expectations'' or ``patterns'' (pattern matching) simultaneously, looking for candidate tracks called ``roads''. This approach reduces to a linear behavior the typical exponential complexity of the CPU based algorithms. Pattern recognition is completed by the time data are loaded into the AM devices. We report on the design of the first Processing Unit prototypes. The design had to address the most challenging aspects of this technology: a huge number of detector clusters (``hits'') must be distributed at high rate with very large fan-out to all patterns (10 Million patterns will be located on 128 chips placed on a single board) and a huge number of roads must be collected and sent back to the FTK post-pattern-recognition functions. A network of high speed serial links is used to solve the data distribution problem.
Highlights
The pattern recognition inside each detector tower is executed by two Processing Unit (PU) working in parallel
We present the first prototype of a new Processing Unit (PU), the core of the FastTracker processor (FTK)
We report on the design of the first Processing Unit prototypes
Summary
When the Control chip starts to process an event, the hits are popped in parallel from all the hit input FIFOs and are simultaneously sent to the four LAMBs. Holds are sent by the AUXFTK to the AMBFTK to stop sending roads if an AUX FIFO receiving one of the road links becomes half full. Once the LAMBs have made the last of the matched roads of the “Nth” event available to the AUXFTK, including the 16 EE words on all the 16 road serial links, the “Nth” event is considered fully processed. (2) All EE words have been received for the “N+1st” event from the 12 serial links coming from the AUX board. 2.5 Proto-AUX The Proto-AUX, pictured, was designed to test the high-speed links to the AMBFTK and VME access to the AUXFTK. It contains two Altera Stratix IV [10] FPGAs, each of which has sixteen 8.5 Gbit/s transceivers. Data integrity will be checked by comparing the received road IDs to the expected IDs corresponding to the sent data
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