Abstract
As one of the core components of electronic hardware systems, Field Programmable Logic Array (FPGA) device design technology continues to advance under the guidance of electronic information technology policies, and has made information technology applications. huge contribution. However, with the advancement of chip technology and the continuous upgrading of information technology, the functions that FPGAs need to perform are more and more complicated. How to efficiently perform layout design and make full use of chip resources has become an important technology to be solved and optimized in FPGA design. The FPGA itself is not limited to a specific function. It contains internal functions such as memory, protocol module, clock module, high-speed interface module and digital signal processing. It can be programmed through logic modules such as programmable logic unit modules and interconnects. Blank FPGA devices are designed to be high performance system applications with complex functions. The layout and routing technology based on cluster logic unit blocks can combine the above resources to give full play to its performance advantages, and its importance is self-evident. Based on the traditional FPGA implementation, this paper analyzes several advantages based on cluster logic block layout and routing technology, and generalizes the design method and flow based on cluster logic block layout and routing technology.
Highlights
Most SRAM-based Field Programmable Logic Array (FPGA) logic cell blocks use a look-up table (LUT) structure [1,2]
This paper explored the following four aspects of cluster structure logic block placement and routing technology: 1 The optimal number of inputs that the FPGA interconnect should assign to each LUT of the logical cluster; 2 The change in the connectivity of the logical block and the interconnect interface when the number of LUTs inside a logical unit block changes; 3 To achieve the best routing speed and area utilization for an FPGA, the number of LUTs should be included in a logic cluster; 4 The time required to compile the circuit is affected by the size of the logical cluster
I input is not connected directly to the Basic Logic Element (BLE), but through a multi-channel selector array, select the LUT after input to the BLE, and the output of the each BLEt is connected to the multi-channel selector array of input, through multi-channel selector control signal, the output of the cluster within any BLE input can be connected to any BLE
Summary
Most SRAM-based FPGA logic cell blocks use a look-up table (LUT) structure [1,2]. The complexity of the internal structure of the LUT increases with the number of inputs. We need to enter more LUTs to reduce the wiring between logic blocks and the interconnection area. On the one hand, merging related LUTs into a single logical unit block can reduce the number of interconnecting networks between logical unit blocks, thereby saving interconnection area. For the logic cluster placement and routing technology, the area occupied by local interconnects increased quadratically with the size of the logic cluster. In this way, for a sufficiently large logical cluster, the area occupied by the local interconnect will exceed the area saved by the global interconnect [13~17]. This paper explored the following four aspects of cluster structure logic block placement and routing technology:
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