The adiabatic anti-jitter circuit

Abstract

The Anti-Jitter Circuit (AJC) uniquely is able to reduce phase noise of any frequency source at sideband frequencies above a defined cut-off frequency. By contrast a Phase Lock Loop (PLL) reduces phase noise closer to carrier lower than a defined frequency. The purpose of this paper is to report several further improvements in the implementation of the AJC in respect of power consumption, frequency range and maximum frequency of operation. The improvements stem mainly from the invention of the AJC, which affords significantly enhanced performance over the AJC previously reported. The term adiabatic is adopted to indicate that the core part of the new circuit does not require a power supply. It takes power from the input source directly to create the sawtooth waveform that has considerably reduced time jitter on the longer of its two ramp waveforms. This paper also reports work that FET (CMOS) technology in general is to be preferred to bipolar technology for the AJC. Discrete models are now operational at 30 MHz, which is twice the 15 MHz operation previously reported. The cut-off frequency of suppression has been maintained at a few kHz. Noise analysis now shows performance comparable to an LC oscillator is possible. SPICE simulations show potential operation up to 5 GHz The AAJC is also cascadable up to the intrinsic shot noise limit. Shot noise can be reduced by feedback.