Abstract

Designing a chip set for a new processor architecture like the IA-64 requires handling multiple aspects. They include implementing the processor interface; providing sufficient I/O bandwidth for servers; supporting accelerated graphics port (AGP) graphics; and providing sufficient memory bandwidth for the processor, I/O, and graphics. This article provides an introduction to the memory, I/O, and graphics subsystems of Intel's Itanium processor chip set and discusses several aspects of the processor bus.

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