The 300 mm silicon wafer — a cost and technology challenge

Abstract

The conversion to 300 mm wafers is strictly cost driven. Cost, capability and timing are still the major challenges during this shaky transition phase. Looking back to 1995, industry consortia decided that the next wafer size would be 300 mm and all major Si manufacturers started to invest in costly 300 mm pilot lines. Even during the recent recession, they poured millions of dollars into the development of the first dummy, mechanical, and furnace wafers. Now 5 years later the first prime wafers with 0.18 μm design rule quality are available and the recession is over — one pilot line of a leading IC manufacturer is already running, proving the readiness of equipment and silicon — several other pilot lines and first fabs are planned in Asia, the USA and in Europe. The first silicon is scheduled for 2000 and 2001 anticipating the use of the 0.13 μm design rule at least. Besides this technological challenge, key-device manufacturers have posed a second challenge to the Si manufacturing community: price parity per square centimeter silicon at a much faster rate than in previous diameter conversions. Now that the 300 mm conversion is revitalized, the goal is to achieve the same area factor at a fraction of the historical number. To achieve these challenging cost and capability goals at the right time, Si manufacturers have to do things differently — they have to shift many paradigms, regarding cost reduction, communication and technology, which is the topic of this paper.