THCMOS: testable high speed CMOS design

Abstract

CMOS circuits present severe. problems in the detection of eansistor stuck-on and transistor stuck-open faults. There is no testing procedure available to detect CMOS stuck-ON faults by logic testing. Such faults are detected by current measurements. CMOS stuck-open faults cause sequential behavior in the circuit and hence, two or multi-pattem sequences =e used to detect s-open faults. Furthermore, two or multi-panem sequences may fail to detect a fault in several situations. The available methods for augmenting CMOS gates require very large amount of exka hardware and still do not detect a fault deterministically. A new design called THCMOS (testable high speed CMOS), is presented. The scheme implements CMOS gates by symmetric n-pan and p-parts, without using any extra msistor to improve the circuit controllability. The proposed design is highly tetable and fault tolerant. The design ensures the detection of stuck-open as well as stuck-ON faults while single test vector is used during testing. Furthermore, the proposed CMOS gates are approximately twice as fast as conventional CMOS gates and hence, very useful for high performance circuits.