Abstract
Resilient circuits with timing error detection and correction (EDAC) can eliminate the excess timing margin but suffer from the short-path (SP) issue where SPs must be padded to exceed the detection window. SP padding (SPP) is similar to, but severer than, hold time fixing. Thus, it incurs significant area overhead, especially when working in the near-threshold region. In this article, we propose a transmission gate-based SPP (TG-SPP) method, which uses only one transmission gate to extend an SP to the negative clock phase while keeping the critical paths unaffected. Compared with the two-phase latch way or the conventional padding with tens to hundreds of buffers in an SP, our method efficiently decreases the overhead. We develop transmission gate insertion rules and an automatic insertion flow to overcome the complicated intersection problem of short and critical paths. To further reduce the EDAC area overhead, we also propose a lightweight error detection latch that has only two extra transistors compared to a conventional 24-T flip-flop for the conventional way. We implement all the proposed techniques in an SHA-256 chip using the 28-nm CMOS process. Results show that our TG-SPP method achieves the same padding effect as the two-phase latch-based method while reducing both the glitch power and sequential area overhead by a factor of 6 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> . The fabricated resilient chips are measured to achieve 55%–405% frequency improvement and 38.6%–69.4% power saving compared with the typical margined baseline at the near-threshold region.
Highlights
D UE to the process, voltage, and temperature (PVT) variations [1]–[5], conservative timing margins or voltage margins are reserved during the design of digital circuits to Manuscript received April 9, 2019; revised July 5, 2019 and September 18, 2019; accepted October 9, 2019
The benefit of this fabrication and direct testing is that the foundry provides multiple wafers with selected process variations of SS, TT, and FF, which are different from multi project wafer (MPW) chips that are around the TT corner
In order to solve the SP issue in the resilient circuit, we propose a controlled transmission gates (CTGs)-based method, which extends SPs with only one CTG gate in a path
Summary
D UE to the process, voltage, and temperature (PVT) variations [1]–[5], conservative timing margins or voltage margins are reserved during the design of digital circuits to Manuscript received April 9, 2019; revised July 5, 2019 and September 18, 2019; accepted October 9, 2019. In situ timing error-detection and correction (EDAC) [4]–[31]-based adaptive voltage frequency-scaling (AVFS) techniques can eliminate such margins while ensuring correct operation across PVT variations. The AVFS system can tune the supply voltage and/or frequency to make the circuit operating on the edge of timing failure These techniques suffer from the short-path (SP) issue because EDLs generate a timing error signal when a signal transition occurs during the detection window (usually the positive clock phase), no matter it is a late-arriving signal from a critical path of the previous cycle or a normal signal from an SP of the current clock cycle.
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