T‐Gate Fabrication of InP‐Based HEMTs Using PMGI/ZEP520A/PMGI/ZEP520A Stacked Resist

Abstract

PMGI/ZEP520A/PMGI/ZEP520A fourlayer resist stack is firstly proposed for T-gates fabrication of InP-based High electron mobility transistors (HEMTs). Gate-head and gate-foot are exposed in single-step Electron beam lithography (EBL), which avoids alignment deviation by automatic self-alignment. The newly introduced PMGI at the bottom greatly improves the adhesiveness of ZEP520A resist with the substrate. The optimal gate-foot length reaches 101nm for a design of 50nm gate footprint pattern, and which can be improved to be 66.8nm for 30nm gate footprint pattern. Finally, Tgates in nanometer regime have been successfully incorporated into InP-based HEMTs fabrication. Benefiting from both the narrow gate-foot and the reduced parasitic gatecapacitance by single-step EBL technique with the fourlayer resist stack, the fabricated devices with gate-foot length of 101nm demonstrate excellent DC and RF performances: the maximum extrinsic transconductance, the current-gain cutoff frequency and maximum oscillation frequency are 1051mS/mm, 249GHz and 415GHz, respectively.