Abstract
This research describes about the testing of virtual reconfigurable circuit (VRC) designed and implemented for a fault tolerant system which averages the (three) sensor inputs. The circuits that are to be tested are those which are successfully evolved in this system under different situations such as (i) all the three sensors are faultless (ii) one of the input sensor fails as open (iii) sensors fails as short circuit. The objective of this research is to test the desired optimal circuits evolved by decoding the configuration bit streams. The logic simulation tool used to perform fault simulation is AUSIM (Auburn University Simulator).
Highlights
VIRTUAL CONFIGURABLE CIRCUITEnsuring the reliability of Electronic Circuits has always been a challenge
We will be interested in faults that can occur within the virtual reconfigurable circuit (VRC), instead of focusing on environmental problems such as temperature, extreme radiation, etc
The fault Tolerant System is evolved using the idea of VRC on FPGA[2] .when the VRC is uploaded in to the FPGA its configuration bit stream determines Processing Elements (PEs) function and the places where its inputs are connected
Summary
VIRTUAL CONFIGURABLE CIRCUITEnsuring the reliability of Electronic Circuits has always been a challenge. AUSIM: Auburn University SIMulator was very useful in testing the architecture of Virtual Reconfigurable Circuit. The fault Tolerant System is evolved using the idea of VRC on FPGA[2] .when the VRC is uploaded in to the FPGA its configuration bit stream determines Processing Elements (PEs) function and the places where its inputs are connected. The VRC designed for this Evolvable Fault Tolerant system consists of 25 Processing Elements (PEs) and are arranged in 4 rows and 6 columns with one output PE.
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