Testing STT-MRAM: Manufacturing Defects, Fault Models, and Test Solutions

Abstract

STT-MRAM is one of the most promising emerging non-volatile memory technologies. As its mass production and deployment in industry is around the corner, high-quality yet cost-efficient manufacturing test solutions are crucial to ensure the required quality of products being shipped to end customers. This paper focuses on STT-MRAM testing, covering three abstraction levels: manufacturing defects, fault models, and test solutions. We first survey STT-MRAM manufacturing defect space and apply the conventional resistor-based test approach to develop test solutions. We then demonstrate with silicon measurements that this approach fails to appropriately model and test defects in STT-MRAM devices: magnetic tunnel junctions (MTJs), although it is qualified for interconnect/contact defects. Therefore, we propose a new test approach: device-aware test (DAT) to specifically target device-internal defects. We apply DAT to three key types of MTJ defects: pinhole, synthetic anti-ferromagnet flip, and intermediate state defects. After developing accurate defect models and calibrating them with silicon data, we perform comprehensive fault analyses based on SPICE circuit simulations to derive accurate and realistic fault models. Some STT-MRAM unique faults are identified, including both permanent faults and intermittent faults. Based on the obtained fault models, high-quality test solutions are proposed. Additionally, this paper also proposes a magnetic coupling model and a magnetic-field-aware compact MTJ model for fast and robust STT-MRAM designs.