Testing of Non-volatile Logic-Based System Chips

Abstract

An non-volatile logic (NVL) -based system chip uses non-volatile storage elements to backup working state of volatile storage elements in sleep mode such that the power of chip can be turned off and zero standby power can be achieved. Since an NVL-based system chip consists of logic circuits and non-volatile storage elements, tests for logic circuits only and for non-volatile memories only are not sufficient for the testing of NVL-based system chips. The interface circuit between the volatile storage element and the non-volatile storage element must be tested as well. This paper presents possible faults occurred in the NVL-based system chips when the backup and restore operations are executed. Then, an effective test method with alternating 0/1 test sequence for detecting the defined backup and restore faults is proposed. In comparison with a straightforward test method, the proposed test method can achieve 41% test time reduction for an NVL-based design with 2537 flip flops.