Testing of in-memory-computing memories with 8 T SRAMs

Abstract

In-memory-computing (IMC) architecture has been proposed as an alternative to cope with the memory wall of von-Neumann computing architecture. The IMC architecture embeds logic into the memory array to reduce the data transfer between the processor and memory. An IMC memory can be operated in memory mode and computing mode, which increases the test complexity. Thus, the IMC memory need to be tested in memory mode and computing mode. In this paper, we propose a test strategy for IMC 8 T SRAMs with NAND and NOR logic operations. Possible functional faults caused by the isolated read port of the 8 T SRAM cell are analyzed. A 12N March C−8 test algorithm is proposed to cover functional faults in memory mode and process variation-induced faults in computing mode of an N-bit IMC 8 T SRAM. Extendibility of the proposed test strategy for 8 T SRAMs and multiple operands is shown as well.