Testing of 3D chips: Is there anything new under the sun?

Abstract

D chips based on Through-Silicon Vias are hot in the design and processing community. What new test challenges do they bring forward, and how much of the learnings from MCM and SIP testing can be applied in this field? Description Three-dimensional chip stacking with Through-Silicon Vias (TSVs) is the hope of the future: where device scaling comes to an end, 3D technology is supposed to still the semiconductor industry's hunger for more functionality, bandwidth, and performance at even smaller sizes, power dissipation, and cost. Whereas 3D stacking received a lot of attention at design, processing, and packaging conferences, it has not made it to a mainstream topic yet at ITC. How should the 3D super chips be tested? Are the conventional test approaches for 2D chips one-on-one applicable to 3D products? Can we leverage learnings from printed-circuit board, multi-chip module, and system-in-package testing? Are there any new, 3D-specific, test challenges left to be addressed? And how do these new products change the industrial food chain? Organizers