Test-Architecture Optimization and Test Scheduling

Abstract

Previous chapters have discussed issues associated with pre-bond KGD test and test standards for pre-bond and post-bond test. Post-bond testing is in many ways a less complex issue than pre-bond test, because external test pins can be utilized for test access and TSVs in bonded dies can be treated as interconnects during test (although testing the TSVs themselves may require testing for failure modes unique to TSVs and neighboring active devices). Nevertheless, new constraints for post-bond testing of a 3D stack must be considered, such as limited test access to dies depending on their position in the stack, multiple post-bond test insertions, and limitations on the addition of test TSVs between dies. Just as for pre-bond test, optimizations are needed to design 3D test architectures and test schedules to minimize the cost of post-bond test in order to achieve cost-effective KGD, partial stack, and known-good-stack (KGS) test throughout the manufacture flow of a product.