Abstract
Checkers are used in digital circuits to detect both intermittent and stuck-at faults. The most common error detectors are parity checkers. Such circuits are themselves subject to failures. The use of parity trees is outlined, and techniques for testing them are surveyed. The effect of the checker's structure on its testability is discussed. Several fault models are considered: single stuck-at, multiple stuck-at, and bridging faults. The effectiveness of single stuck-at fault test sets in detecting multiple stuck-at and bridging faults is described. Upper bounds for the double fault coverage of the minimal single fault test are given for different tree structures. The testabilities of some selected checkers are examined to illustrate the concepts developed. A built-in self-test is proposed.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
