Testability analysis in a VLSI high-level synthesis system

Abstract

This paper deals with the problem of defining testability measures for register-transfer level designs in order to incorporate them into the high-level synthesis system of VLSI circuits. First, a design representation and its observability and controllability measures are defined. Second, an algorithm for testability analysis is described. Third, some discussion about how the testability measures can be used to influence the synthesis process is given. Finally, some practical impact and applications of the presented approach are also indicated.