Abstract
Advancement of VLSI technology helps semiconductor industry to manufacture Through-silicon-via (TSV) based 3D stacked ICs (SICs). During 3D assembly, multiple partial stack tests are necessary. This paper addresses test architecture optimization for 3D stacked ICs based on multiple towers with hard dies. Two different handcrafted 3D SICs comprising of SOCs from ITC'02 benchmarks are considered and overall test time is minimized based on three algorithms -- layer-by-layer, tower-by-tower and a heuristic algorithm that are presented in this paper.
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